1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a clock synchronous semiconductor memory device that operates in synchronization with a clock signal. More particularly, the present invention relates to the structure of an internal data transfer scheme of a clock synchronous semiconductor memory device that can switch the word configuration.
2. Description of the Background Art
FIG. 58 schematically shows an entire structure of a conventional synchronous semiconductor memory device. Referring to FIG. 58, a synchronous semiconductor memory device 900 includes memory arrays MAa, MAb, MAc and MAd each having a plurality of memory cells arranged in rows and columns, multibit internal data buses 910a-910d provided corresponding to memory arrays MAa, MAb, MAc and MAd, respectively, a selector/driver 915 selecting bus lines of multibit internal data buses 910a-910d according to an address signal CA and a select signal .phi.sel, an internal read data bus 920 transmitting data from selector/driver 915, and an output circuit OB generating external data according to data applied through internal read data bus 920.
Memory arrays MAa-MAd form banks #0-#3, respectively, and are driven to a selected state independent of each other. Here, "a selected state" refers to the state where a word line is driven to a selected state in a memory array and the data in a memory cell connected to the selected word line is retained.
Select signal .phi.sel is set selectively and fixedly according to the bit width of output data DQ from output circuit OB. One chip can accommodate a plurality of word configurations such as .times.4, .times.8, .times.16 and .times.32 bits.
The reason why multibit internal data buses 910a-910d are provided corresponding to memory arrays MAa-MAd, respectively, is described in the following. Banks #0-#3 are driven to a selected state independent of each other, so that a plurality of banks can be maintained at a selected state. However, the access operation of writing/reading data with respect to a memory cell is carried out for one bank. The number of these banks can be altered. Therefore, internal data buses 910a-910d are provided corresponding to memory arrays MAa-MAd, respectively, in order to readily accommodate an arbitrary bank configuration. The bit width of internal data buses 910a-910d is equal to the bit width of internal read bus 920. Selector/driver 915 selects an internal data bus according to a selected bank to be coupled to internal read data bus 920. Selector/driver 915 is responsive to select signal .phi.sel and address signal CA for switching the bus connection path according to a bit width of output data DQ.
FIG. 59 schematically shows a structure of selector/driver 915. The circuitry for one internal data bus is shown as a representative in FIG. 59. Internal data bus 910 (910a.about.910d) includes bus lines 910-0.about.910-3 of 4 bits. The output data of preamplifiers 925-0.about.925-3 that amplify memory cell data IO0-IO3 are transmitted to data bus lines 910-0.about.910-3, respectively.
Similarly, read data bus 920 includes read data bus lines 920-0.about.920-3 of 4 bits. Output circuits OB0-OB3 are provided for these read data bus lines 920-0.about.920-3, respectively. Output data DQ0-DQ3 are provided from output circuits OB0-OB3, respectively.
Selector/driver 915 includes an OR circuit 915a receiving address signal CA and select signal .phi.sel, an inverter 915b inverting the output signal of OR circuit 915a, drive circuits DV0-DV3 provided corresponding to read data bus lines 920-0.about.920-3, respectively, a transfer gate TX0 coupling data bus line 910-0 to the input of drive circuit DV1 according to the output signal of inverter 915b, a transfer gate TX1 coupling data bus line 910-1 to the input of drive circuit DV1 according to the output signal of OR circuit 915a, a transfer gate TX2 coupling data bus line 910-2 to the input unit of data circuit DV3 according to the output signal of inverter 915b, and a transfer gate TX3 coupling data bus line 910-3 to the input of drive circuit DV3 according to the output signal of OR circuit 915a. Drive circuits DV0 and DV2 are enabled when select signal .phi.sel is at an H level (logical high), to drive read data bus lines 920-0.about.920-2 according to the data read out on data bus lines 910-0 and 910-2.
Select signal .phi.sel indicates a .times.4-bit configuration and a .times.2-bit configuration for the word configuration (number of output data bits) at an H level and an L level Logical low), respectively. The operation of selector/driver 915 of FIG. 59 will be described briefly now.
When the word configuration corresponds to a .times.4-bit configuration, select signal .phi.sel is fixed at an H level. In this state, the output signal of OR circuit 915a is at an H level. Transfer gates TX1 and TX3 are conductive, and transfer gates TX0 and TX2 are non-conductive. Also, drive circuits DV0 and DV2 are set at an operable state. Therefore, read data bus lines 920-0.about.920-3 are driven by drive circuits DV0-DV3 according to the data transmitted through data bus lines 910-0.about.910-3, whereby 4 bits of data DQ0-DQ3 are output via output circuits OB0-OB3.
When select signal .phi.sel is at an L level, drive circuits DV0 and DV2 are set at operation disabled state. Under this state, transfer gates TX0-TX3 are selectively rendered conductive according to the H level/L level of address signal CA. When address signal CA is at an H level, OR circuit 915a provides an output signal of an H level. Transfer gates TX1 and TX3 are rendered conductive. Data bus lines 910-1 and 910-3 are coupled to drive circuits DV1 and DV3, respectively. Therefore, memory cell data IO1 and IO3 are transmitted to output circuits OB1 and OB3, respectively, whereby data DQ1 and DQ3 are generated. When address signal CA is at an H level, transfer gates TX1 and TX3 are rendered non-conductive, whereas transfer gates TX0 and TX2 are rendered conductive. Data bus lines 910-0 and 910-2 are coupled to drive circuits DV1 and DV3, respectively. In this case, memory cell data IO0 and IO2 are transmitted to output circuits OB1 and OB3, whereby data bits DQ1 and Q3 are generated. As a result, data of a 2-bit configuration is output. Output circuits OB0 and OB2 are set at a non-operable state when the word configuration corresponds to a .times.2-bit configuration.
By employing selector/driver 915 shown in FIG. 59, a plurality of word configurations can be accommodated without modifying the internal circuit configuration.
When data buses are arranged corresponding to respective memory arrays MAa-MAd as shown in FIG. 58, the area occupied by the data buses increases. Particularly in the case where the word configuration is as large as .times.16 bits or .times.32 bits, the area occupied by the buses becomes large. In a case of switching the bus connection according to the word configuration by use of selector/driver 915, signal propagation is delayed in the transfer gate that switches the connection, leading to a problem that a signal cannot be transmitted at high speed. Particularly in the case where the word configuration is switched between .times.16 bits and .times.32 bits, the number of the transfer gates for this selector/driver is increased to result in a larger occupying area. When the number of word configurations that can be selected is increased so that any of .times.4, .times.8, and .times.16, can be selected, the selector/driver requires the select operation of three stages, i.e. the selection of 16 bits from 32 bits, the selection of 8 bits from 16 bits, and the selection of 4 bits from 8 bits. The occupying area of this selector/driver is increased, which further delays the signal propagation. Therefore, data can not be read out at high speed.
Such a selector/diver is also provided for the data write path. Thus, there is a similar problem that data cannot be transmitted to a selected memory cell at high speed.
In a clock synchronous semiconductor memory device, an operation parameter called "CAS latency" is present. This is the number of cycles of the clock signal required from the application of an access command (a read command designating data reading or a write command designating data writing) up to the actual writing of data into a memory cell or actual data read out. Internally, the circuitry is driven according to this CAS latency. Therefore, address signal CA for the selector/driver must have the activation timing modified according to this CAS latency in the structure of FIG. 59, resulting in discrepancy between the ascertained timing of address signal CA and the ascertained timing of the output data from preamplifiers 925-0.about.925-3. Therefore, the issue of timing margin must be considered, and data cannot be read out at high speed. The same applies for data writing.